http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-19990080854-A
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-285 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32137 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76819 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31138 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02271 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate | 1998-04-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 1999-11-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-19990080854-A |
| titleOfInvention | Method for manufacturing contact hole of semiconductor device |
| abstract | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a contact hole in a semiconductor device, wherein a polysilicon layer having a high etching selectivity is used as an etch barrier in a self-aligned contact (SAC) process due to an overlay margin problem. And isotropically etched away the polysilicon layer used as the etch stop layer, and then reflow BPSG or deposit a mesophilic oxide layer to prevent electrical shorts between the microwires caused by the polysilicon layer. It is a technology to improve the characteristics and reliability of semiconductor devices. |
| priorityDate | 1998-04-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID425193155 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419579069 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID783 |
Total number of triples: 19.