http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-19990076267-A
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4076 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-1252 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-133 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-00 |
| filingDate | 1998-03-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 1999-10-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-19990076267-A |
| titleOfInvention | Clock Synchronous Delay Circuit Using Differential Clock Signal |
| abstract | A clock synchronizing delay circuit using a differential clock signal is disclosed. A clock synchronous delay circuit using a differential clock signal according to the present invention inputs a differential clock signal externally applied and delays it by a first delay time, and buffers the delayed result to output the first clock signal and the first complementary clock signal. A differential clock buffer, a dummy delay means for delaying the first clock signal by a second delay time and outputting the delayed signal as a second clock signal, a plurality of serially connected unit delay means, and inputting a second clock signal A first clock delay means for outputting third clock signals having different delay times corresponding to a combination of unit delay means, and comparing the phase of the first clock signal and the third clock signals to match the phase of the first clock signal. A comparison means for latching the third clock signal as the fourth clock signal and generating first and second control signals in response to the latched result; A second clock delay means having the above delay means, delaying the first clock signal by a third delay time corresponding to the first and second control signals, and outputting the fifth clock signal as a fifth clock signal; A complementary clock delay means for delaying the first complementary clock signal by a third delay time and outputting the fifth complementary clock signal as a fifth complementary clock signal, a clock driver for delaying the fifth clock signal by a fourth delay time and outputting the internal clock signal; And a complementary clock driver that delays the fifth complementary clock signal by a fourth delay time and outputs the internal complementary clock signal. |
| priorityDate | 1998-03-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 50.