http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-19990029791-A
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-103 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-12 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-41 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-413 |
| filingDate | 1998-09-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 1999-04-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-19990029791-A |
| titleOfInvention | Semiconductor integrated circuit device |
| abstract | The semiconductor integrated circuit device includes a main memory unit including a plurality of columns and a plurality of memory cells arranged in a plurality of rows, and a sub memory unit including a plurality of columns and a plurality of memory cells arranged in a plurality of rows. One or more address input terminals for specifying a negative row or column and one or more address input terminals for specifying a row or a column of the sub memory part are commonly used, and the total number of address input terminals specifies a row or a column of the main memory part. It is less than or equal to the number of address input terminals. Thus, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processing devices. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100863716-B1 |
| priorityDate | 1997-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 54.