http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-19980064093-A

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filingDate 1997-12-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 1998-10-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-19980064093-A
titleOfInvention Semiconductor integrated circuit device and its manufacturing method
abstract Using the same photoresist pattern as a mask, the source and drain regions of the n-channel MOSFET 3n, the p-type semiconductor region 4p for suppressing the short channel effect, and the n well feed region 10n are formed in the semiconductor substrate 1. A process of implanting impurity ions for a source, a source / drain region of a p-channel MOS-FET 3p, an n-type semiconductor region 4n for suppressing short channel effects, and the like on the semiconductor substrate 1 using the same photoresist pattern as a mask; and implanting impurity ions for forming the p well power supply region 10p.n n n It is a manufacturing method of a semiconductor integrated circuit device in which an n-channel MIS transistor and a p-channel MIS transistor are provided on the same semiconductor substrate.
priorityDate 1996-12-13-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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