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filingDate 1996-12-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 1998-09-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-19980044102-A
titleOfInvention Method for forming contact plug of semiconductor device
abstract The present invention discloses a method for forming a contact plug of a semiconductor device.n n n A first embodiment of the present invention includes a first step of sequentially forming a first insulating film and a second insulating film by depositing an insulating material on a semiconductor substrate having a wiring layer; A second step of etching back until the second insulating film is completely removed; A third step of forming a third insulating film on the first insulating film; A fourth step of forming a contact hole by etching the third insulating film / first insulating film so that the surface of the wiring layer is exposed; A fifth step of forming a barrier layer according to the structure of the resultant product formed in the above steps; A sixth step of forming a material layer by depositing any one of a low resistance metal, a compound including the same, and polycrystalline silicon on the entire surface of the semiconductor substrate on which the barrier layer is formed; The chemical mechanical polishing (CMP) method is used to grind the material layer and the barrier layer until the third insulating film is exposed. A second embodiment of the present invention includes a first step of sequentially forming a first insulating film and a second insulating film by depositing an insulating material on a semiconductor substrate having a wiring layer; A second step of etching back until the second insulating film is completely removed; A third step of forming a third insulating film on the first insulating film; A fourth step of forming a trench by removing a predetermined thickness of a third insulating layer on the wiring layer; A fifth step of forming a contact hole by etching the third insulating film / first insulating film so that the surface of the wiring layer is exposed; A sixth step of forming a barrier layer according to the structure of the resultant product formed in the above steps; A seventh step of forming a material layer using any one of a low resistance metal, a compound including the same, and polycrystalline silicon on the entire surface of the semiconductor substrate on which the barrier layer is formed; And an eighth step of polishing the material layer and the barrier layer until the third insulating film is exposed using a chemical mechanical polishing (CMP) method. In other words, the insulating film is planarized by etching back instead of chemical mechanical polishing, and the insulating layer and the insulating film are in-situ polished to form a plug using a chemical mechanical polishing apparatus having two or more polishing plates. In addition to simplifying and improving flatness, there is an advantage in that a plug and another wiring layer can be simultaneously formed on the wiring layer.
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priorityDate 1996-12-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 39.