Predicate |
Object |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42368 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0873 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-518 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-324 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-34 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66734 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-31 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4236 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-053 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66621 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
filingDate |
2018-02-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2022-10-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationDate |
2022-10-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
KR-102457515-B1 |
titleOfInvention |
Semiconductor device having buried gate structure and method for manufacturing the same |
abstract |
The present technology relates to a semiconductor device capable of improving gate-induced drain leakage and a method for manufacturing the same, and the semiconductor device according to the present technology includes: a substrate; a first source/drain region and a second source/drain region formed to be spaced apart from each other by a trench in the substrate; and a gate structure in the trench, wherein the gate structure includes: a gate insulating layer formed on a bottom surface and sidewalls of the trench; a first gate electrode positioned at the bottom of the trench on the gate insulating layer; a second gate electrode positioned on the first gate electrode; and a dipole inducing layer formed between the first gate electrode and the second gate electrode and between sidewalls of the second gate electrode and the gate insulating layer. |
priorityDate |
2018-02-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |