| abstract |
A transistor comprising vertically aligned two-dimensional material is disclosed. The disclosed transistor includes a two-dimensional material provided on a substrate, source and drain electrodes connected to both ends of the two-dimensional material, a gate insulating layer provided on the two-dimensional material, and a gate electrode provided on the gate insulating layer . Here, the two-dimensional material includes at least one layer aligned substantially perpendicular to the substrate, and each layer includes a semiconductor having a two-dimensional shape crystal structure. |