| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32145
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15192
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-04042
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-0401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48091 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0652
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-3452
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K1-111
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-4611
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3128
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-06 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K1-11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-46
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-34 |
| filingDate |
2015-10-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-08-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2022-08-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-102434435-B1 |
| titleOfInvention |
Printed circuit board and semiconductor package having the same |
| abstract |
Provided are a printed circuit board capable of reducing the size of a semiconductor package and a semiconductor package having the same. The printed circuit board according to the present invention includes a substrate base having a chip attachment region on its upper surface, upper and lower pads respectively disposed on the upper and lower surfaces of the substrate base, and a first formed on the upper surface of the substrate base and corresponding to the upper surface pad A first top solder resist layer having a pad opening and covering the chip attachment region, a second top solder resist layer formed on the first top solder resist layer, the second having a second pad opening corresponding to the top pad and a chip attachment opening corresponding to the chip attachment region and a bottom solder resist layer formed on the bottom surface of the substrate base and having a third pad opening corresponding to the bottom pad. |
| priorityDate |
2015-10-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |