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filingDate 2016-08-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2022-08-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2022-08-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-102428605-B1
titleOfInvention Methods for assembling microelectronic components and wafer level packages
abstract Capacitive coupling of integrated circuit die components and other conductive regions is provided. Each component to be joined has a surface comprising at least one conductive region, such as a metal pad or plate. An ultra-thin layer of dielectric is formed on at least one surface to be bonded. When two components, eg, from each die, are permanently contacted together, an ultra-thin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive regions of the respective component. The ultrathin layer of dielectric may be comprised of multiple layers of various dielectrics, but in one implementation, the total thickness is less than approximately 50 nanometers. The capacitance per unit area of the formed capacitive interface depends on the specific dielectric constants κ of the dielectric materials used in the ultrathin layer and their respective thicknesses. Electrical and ground connections may be made at the edge of the combined stack.
priorityDate 2015-09-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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