http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102404638-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2330-021 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0297 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0286 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0291 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0289 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3611 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-356017 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3648 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-012 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-412 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-356139 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-018521 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-0013 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3233 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36 |
| filingDate | 2017-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2022-06-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2022-06-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-102404638-B1 |
| titleOfInvention | Semiconductor device and electronic device |
| abstract | The present invention provides a level shift circuit that operates stably. It has a level shift circuit having first to fourth transistors and a buffer circuit, and one of the source and drain (S/D) of the first transistor is connected to one of the S/D of the second transistor, and the S of the second transistor The other of /D is connected to one of S/D of the third transistor, and the gates of the first transistor and the fourth transistor are connected to the other of S/D of the second transistor and one of S/D of the third transistor connected, a gate of the third transistor is connected to a wiring to which an input signal is input, an input terminal of the buffer circuit is connected to one of S/D of the fourth transistor, and an output terminal of the buffer circuit is connected to the gate of the second transistor and A semiconductor device connected to a wiring through which an output signal is output is provided. |
| priorityDate | 2016-09-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 35.