http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102395193-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8828 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8825 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L45-122 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-063 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-231 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8416 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L45-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L45-1253 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L45-1233 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-826 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8413 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-80 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-84 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-24 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L45-00 |
| filingDate | 2015-10-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2022-05-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2022-05-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-102395193-B1 |
| titleOfInvention | Memory device and method of manufacturing the same |
| abstract | The memory device includes: a plurality of lower word lines extending in a first direction parallel to a top surface of the substrate on a substrate; a plurality of common bit lines extending in a second direction different from the first direction and parallel to a top surface of the substrate on the plurality of lower word lines; a plurality of upper word lines extending in the first direction on the plurality of common bit lines; A plurality of first memory cell pillars disposed at a plurality of intersection points of the plurality of lower word lines and the plurality of common bit lines, each of which includes a first selection element having an ovonic threshold switching characteristic and a first memory layer; ; and a plurality of second memory cells disposed at a plurality of intersection points of the plurality of upper word lines and the plurality of common bit lines, each of which includes a second selection element and a second memory layer each having an ovonic threshold switching characteristic. and a pillar, wherein the plurality of first memory cell pillars and the plurality of second memory cell pillars have a symmetric structure along a third direction perpendicular to the first direction with respect to the plurality of common bit lines. |
| priorityDate | 2015-10-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 37.