| abstract |
Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets are connected to the active base die through their core level conductors. These native interconnects provide short data paths that eliminate the overhead of standard interfaces. The system saves on rewiring routing as native interconnects are coupled in place. The base die may include custom logic that allows the attached dies to provide stock functions. The architecture may connect various interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for driving. Functional blocks mounted on the base die receive native signals from the various chiplets and communicate with all attached chiplets. Chiplets may share processing and memory resources of the base die. Routing blockage is minimized, improving signal quality and timing. The system can operate at dual or quad data rates. This architecture facilitates ASIC, ASSP, and FPGA ICs and neural networks, reducing footprint and power requirements. |