http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102392556-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76873 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76805 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-788 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76852 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788 |
| filingDate | 2019-04-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2022-05-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2022-05-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-102392556-B1 |
| titleOfInvention | Method of manufacturing semiconductor devices |
| abstract | The present invention provides the steps of forming an epitaxial layer and a ground pad on the front surface of a substrate, forming a via hole exposing the ground pad by etching the substrate and a region of the epi layer, and the rear surface of the substrate and the ground Forming a plating layer for electrically connecting the pad, wherein the forming of the plating layer includes a photoresist pattern that covers the back surface of the substrate and exposes the via hole on the inner bottom and inner wall surface of the via hole. Disclosed is a method of manufacturing a semiconductor device comprising: forming a first plating layer; and forming a second plating layer on the first plating layer and a rear surface of the substrate after removing the photoresist pattern. |
| priorityDate | 2018-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.