http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102370741-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1606 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-16 |
| filingDate | 2020-07-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2022-03-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2022-03-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-102370741-B1 |
| titleOfInvention | Ternary Logic Device using Heterojunction-based Multi-layer Channel |
| abstract | A ternary logic device according to an embodiment of the present invention includes a first transistor and a second transistor, the first transistor comprising: a first substrate; a first channel layer positioned on the first substrate; and first source and drain electrodes respectively positioned at opposite ends of the first channel layer, wherein the second transistor includes: a second substrate; an insulating film positioned on the second substrate; a heterojunction-based multilayer channel formed by sequentially stacking a lower semiconductor material layer, a graphene layer, and an upper semiconductor material layer on the insulating film; a second source electrode and a second drain electrode positioned on both sides of the multi-layered channel on the insulating layer, one end of the graphene layer being electrically connected to the second drain electrode, the upper semiconductor material layer One end is electrically connected to at least the second source electrode, one end of the lower semiconductor material layer is electrically connected to at least the second drain electrode, and the first transistor and the second transistor are connected in parallel to form a ternary It can be formed to implement a logical state. Such a ternary logic device can operate as a ternary logic device with excellent operating performance capable of expressing three states by using a heterojunction-based multilayer channel using graphene. |
| priorityDate | 2020-07-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 60.