http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102365487-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0286 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-188 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-184 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3648 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3688 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C19-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36 |
| filingDate | 2021-01-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2022-02-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2022-02-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-102365487-B1 |
| titleOfInvention | Semiconductor device |
| abstract | The present invention suppresses the stress on the transistor while suppressing the occurrence of an operation failure. A pulse output circuit having a function of outputting a pulse signal and having a transistor for controlling whether to set the pulse signal to a high level, wherein, during a period when the pulse signal output from the pulse output circuit is at a low level, a gate of the transistor Instead of maintaining the potential at a constant value, it is made intermittently higher than the potential VSS. In this way, stress on the transistor is suppressed. |
| priorityDate | 2012-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 69.