| abstract |
Various embodiments of the present disclosure are directed to an integrated circuit (IC) chip that includes a semiconductor device that is inverted and overlies a dielectric region embedded on top of a semiconductor substrate. The interconnect structure overlies the semiconductor substrate and the dielectric region and further includes an intermetallic dielectric (IMD) layer. An IMD layer is coupled to the top of the semiconductor substrate and receives the pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is within the semiconductor layer and between the semiconductor layer and the interconnect structure. The semiconductor device overlies the dielectric region and further includes a first source/drain electrode overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance, thereby reducing substrate power loss, and may be, for example, a cavity or a dielectric layer. Contacts extend through the semiconductor layer to the pad. |