| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76883
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76843
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3212
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0273
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0228
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0274
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76829
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7684
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02208
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02216
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76811
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76808
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76813
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31111 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-027
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
2017-06-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-11-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2021-11-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-102331718-B1 |
| titleOfInvention |
Methods of manufacturing a semiconductor device |
| abstract |
In the method of manufacturing a semiconductor device, a first interlayer insulating layer accommodating lower wirings having exposed top surfaces thereon may be formed on a substrate. A second interlayer insulating layer may be selectively formed only on the upper surface of the first interlayer insulating layer. A first etch stop layer and a third interlayer insulating layer may be sequentially formed on the lower interconnections and the second interlayer insulating layer. a trench penetrating an upper portion of the third interlayer insulating film, a first via hole penetrating a lower portion of the third interlayer insulating film and a portion of the first etch stop film to communicate with the trench thereon; and A lower portion of the third interlayer insulating layer and a portion of the first etch stop layer are exposed to expose a top surface of the first wiring among the lower wirings, and the width is smaller than that of the first via hole while communicating with the first via hole. A second via hole having a An upper interconnection filling the trench and vias filling the first and second via holes may be formed. |
| priorityDate |
2017-06-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |