http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102314689-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0291 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-0413 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0278 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0205 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-0404 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3266 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2230-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0286 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-356026 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3648 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3677 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G5-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3696 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36 |
| filingDate | 2021-04-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2021-10-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2021-10-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-102314689-B1 |
| titleOfInvention | Pulse generation circuit and semiconductor device |
| abstract | An object of the present invention is to narrow a bezel width of a display device by designing a layout of a gate driver. Two gate drivers are provided on the left and right sides of the pixel portion. The gate lines are alternately connected to the left and right gate drivers for every M row. The two gate drivers have a shift register and a demultiplexer composed of a single conductivity type transistor. The shift register has k first unit circuits that are cascaded. The demultiplexer has k second unit circuits to which signals are input from the first unit circuits and to which M gate lines are connected. The second unit circuit selects one or a plurality of wirings for outputting the input signal from the first unit circuit from the M gate lines, and outputs the signal from the first unit circuit to the selected wiring. Since the gate signal can be output to the M gate lines from the output of the shift register in one stage, the width of the shift register can be narrowed. |
| priorityDate | 2013-04-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 76.