http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102310122-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2027-11874 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76813 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76811 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60 |
| filingDate | 2014-06-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2021-10-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2021-10-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-102310122-B1 |
| titleOfInvention | Logic cell, integrated circuit including logic cell, and methods of manufacturing the same |
| abstract | The logic cell includes a plurality of conductive regions formed at a first level on the substrate, a first conductive region extending in a first direction at a second level higher than the first level on the substrate, and connected to a first conductive region selected from among the plurality of conductive regions through via contacts. A first wiring layer connected to each other, and a second wiring layer extending in a second direction intersecting the first direction at a third level higher than the second level on the substrate and connected to a second conductive region selected from among a plurality of conductive regions and a deep via contact extending from the second conductive region to the second wiring layer at a position spaced apart from the first wiring layer. |
| priorityDate | 2014-06-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 38.