http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102185278-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-2272 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-085 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0812 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-00 |
| filingDate | 2013-09-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2020-12-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2020-12-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-102185278-B1 |
| titleOfInvention | Clock synchronization circuit and semiconductor memory device comprising thereof |
| abstract | Disclosed are a clock synchronization circuit including a delay locked loop and a semiconductor memory device including the same. The clock synchronization circuit according to an embodiment of the present invention delays an input clock to generate an output clock, and performs a delay fixing operation to lock the input clock and the output clock. And a delay fixing control unit determining whether the locking state continues and ending the delay fixing operation. |
| priorityDate | 2013-04-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 42.