http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102147864-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02J7-00302 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K2217-0018 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K2217-0036 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02J7-00306 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02J7-00304 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K17-162 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0251 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02J7-0029 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0274 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0266 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-535 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02J7-00306 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K17-063 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02J7-0031 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H02J7-00 |
| filingDate | 2017-07-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2020-08-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2020-08-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-102147864-B1 |
| titleOfInvention | Protection ic and semiconductor integrated circuit |
| abstract | It suppresses leakage current caused by parasitic transistors. A bias output terminal connected to the back gate of the MOS transistor, a load-side terminal connected to the power path between a load and the MOS transistor, a load-side switch and a secondary inserted in the current path connecting the bias output terminal and the load-side terminal And a control circuit for outputting a back gate control signal for controlling the back gate potential from the bias output terminal by operating the load-side switch according to the state of the battery, wherein the load-side switch is formed on an N-type silicon substrate, A protection IC comprising at least two NMOS transistors having drains connected to each other, wherein the control circuit simultaneously turns on or off the two NMOS transistors according to a state of the secondary battery. |
| priorityDate | 2016-07-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.