http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102108572-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1248 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78636 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78606 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-564 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2012-09-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2020-05-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2020-05-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-102108572-B1 |
| titleOfInvention | Semiconductor device and method for manufacturing the same |
| abstract | An object of the present invention is to provide a semiconductor device in which electrical property degradation due to moisture is suppressed and a method for manufacturing the semiconductor device. A structure in which a metal oxide layer is located in contact with an interlayer insulating layer covering a transistor is used, and the metal oxide layer is a stacked structure including a first metal oxide layer having an amorphous structure and a second metal oxide layer having a polycrystalline structure. The first metal oxide layer having an amorphous structure is easy to trap moisture between the lattices because there are no grain boundaries and the lattice spacing is wide compared to the crystalline metal oxide layer. The second metal oxide layer having a polycrystalline structure has a dense structure with respect to the crystalline portion to remove the grain boundary portion, and the moisture permeability is very low. Thereby, the structure in which the metal oxide layer including the first metal oxide layer and the second metal oxide layer is in contact with the interlayer insulating layer can effectively prevent moisture from entering the transistor. |
| priorityDate | 2011-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 49.