http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102091350-B1

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-177
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-173
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-0944
filingDate 2019-05-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2020-03-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2020-03-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-102091350-B1
titleOfInvention Programmable logic device
abstract The present invention provides a PLD in which a configuration memory is formed by a nonvolatile memory comprising a small number of transistors, and the arrangement area of the configuration memory is reduced. In addition, it provides a PLD that is easy to respond to dynamic reconstruction and has a high startup time. It is a programmable logic device having a memory element, a selector, and an output portion, and the memory element has a transistor in which a channel is formed in an oxide semiconductor film, a storage capacitor and an inverter connected to one of the source and drain of the transistor, and the inverter is a selector. Connected, the selector provides a programmable logic device connected to the output.
priorityDate 2012-05-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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