| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B41N2210-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B41N2210-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T156-10 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B41F17-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B41N10-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0332
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B41F3-46
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66439 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-775 |
| filingDate |
2013-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2019-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-102031709-B1 |
| titleOfInvention |
Nanowire transistor fabrication with hardmask layers |
| abstract |
The nanowire devices of the present technology provide at least one nanowire to help protect the top channel nanowires from damage that may result from fabrication processes such as those used in replacement metal gate processes and / or nanowire release processes. It can be manufactured by integrating at least one hard mask during the manufacture of the wire transistor. The use of at least one hardmask can result in substantially intact top channel nanowires in the multi-layered nanowire transistors, which can improve the uniformity of the channel nanowires and the reliability of the overall multi-layered nanowire transistors. |
| priorityDate |
2013-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |