http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102010393-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-136231 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-134363 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-1362 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-1343 |
| filingDate | 2013-04-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2019-08-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2019-08-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-102010393-B1 |
| titleOfInvention | Array substrate for in-plane switching mode liquid crystal display device and method of fabricating the same |
| abstract | A method of manufacturing an array substrate for a transverse electric field type liquid crystal display device according to the present invention includes: a first mask process step of forming a gate wiring extending in one direction on a substrate and a gate electrode connected to the gate wiring and the gate wiring; Forming a gate insulating film over the gate wiring and the gate electrode; Stacking a pure amorphous silicon layer, an impurity amorphous silicon pattern, and a conductive metal layer on the gate insulating layer; A second mask process step of forming a source drain pattern and a data line over the gate insulating layer, the active layer overlapping the gate electrode and the impurity amorphous silicon pattern; Forming a first transparent conductive material layer over the source drain pattern; An ohmic contact layer formed on the first transparent conductive material layer to be spaced apart from each other by removing the source and drain electrodes, the pixel electrode in direct contact with the drain electrode, and the impurity amorphous silicon pattern exposed between the source and drain electrodes A third mask process step of forming a; A fourth mask process step of forming a protective film on the entire surface of the substrate; And a fifth mask process step of forming a common electrode on the passivation layer. |
| priorityDate | 2013-04-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 35.