http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101889469-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-518 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-495 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02576 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02532 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02148 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28202 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28247 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02579 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02274 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823828 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate | 2011-10-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2018-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2018-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-101889469-B1 |
| titleOfInvention | Complementary metal oxide semiconductor integrated circuit with metal gate and high―k dielectric |
| abstract | The present invention relates to a semiconductor device capable of independently adjusting a threshold voltage of an NMOS transistor and a threshold voltage of a PMOS transistor during a CMOS integration process and a method of manufacturing the same. An NMOS gate stacked body and a PMOS gate stacked body including a metal layer on the gate dielectric layer and a capping layer on the metal layer; A plurality of germanium contained in the P-type channel below the PMOS gate stack to control a threshold voltage of the PMOS; And a plurality of arsenic formed at the interface between the metal layer and the capping layer of the NMOS gate stack to control the threshold voltage of the NMOS, wherein the arsenic reduces the threshold voltage of the NMOS and the lowermanium reduces the threshold voltage of the PMOS . |
| priorityDate | 2011-10-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 58.