http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101874144-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0895 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-1028 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02P70-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-037 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-84 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-185 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C14-0054 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-356 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C14-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-185 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C14-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-037 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-356 |
| filingDate | 2012-04-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2018-07-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2018-07-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-101874144-B1 |
| titleOfInvention | Semiconductor memory device |
| abstract | A semiconductor memory device includes a memory circuit including a transistor including an oxide semiconductor in a semiconductor layer; A capacitor element for storing charges for reading data held in the memory circuit; A charge accumulation circuit for controlling the accumulation of charges in the capacitor element; A data detection circuit for controlling readout of data; A third signal for delaying the second signal of the power supply voltage and the second signal of the power supply voltage in a period immediately after the power supply voltage is supplied as a first signal for controlling the accumulation of the charge to the capacitive element performed by the charge storage circuit, A timing control circuit for generating a first signal generated by a signal; And an inverter circuit for outputting a potential obtained by inverting the potential of one electrode of the capacitive element. |
| priorityDate | 2011-05-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 73.