| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2029-7858
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78618
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7842
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7851
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1079
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0669
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66439
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2011-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2018-01-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2018-01-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-101821672-B1 |
| titleOfInvention |
Non-planar gate all-around device and method of fabrication thereof |
| abstract |
A non-planar gate allround device and its fabrication method are described. In one embodiment, the apparatus comprises a substrate having an upper surface with a first lattice constant. Embedded epitaxial and drain regions are formed on the top surface of the substrate. The embedded epitaxial source and drain regions have a second lattice constant different from the first lattice constant. Channel nanowires with a third lattice constant are formed and coupled between the embedded epi source and drain regions. In one embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include the bottommost channel nanowire and bottom gate isolation is formed below the bottommost channel nanowire on the top surface of the substrate. A gate dielectric layer is formed on each and every channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounds the channel nanowire. |
| priorityDate |
2011-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |