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filingDate 2011-03-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2017-10-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2017-10-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-101790320-B1
titleOfInvention Divider circuit
abstract The operation failure of the frequency dividing circuit is suppressed. A shift register for generating and outputting a pulse signal of 2 x X (where X is a natural number of 2 or more) according to the first or second clock signal; And a divided signal output circuit for generating and outputting a signal to be a third clock signal which is a cycle of the first to Xth pulse signals, A first transistor for controlling whether or not a voltage of a signal to which a different pulse signal is input and which becomes a third clock signal is set to a first voltage; And X second transistors for controlling whether or not to set the voltage of a signal to which different pulse signals are inputted and the third clock signal to be a second voltage among the 2 x X th pulse signals.
priorityDate 2010-04-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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