| abstract |
The SSD controller maintains a count of 0 and a count of 1, and / or, in some embodiments, a 0/1 mismatch count, for each read unit read from the SLC NVM (or lower page of the MLC). In the event that the read unit becomes uncorrectable due to the partial threshold voltage distribution moving away from their nominal distribution, the held counts will track the threshold voltage shift and adjust the read threshold to recover the read data 0/1 balance Direction and / or size of the image. In various embodiments, the adjusted read threshold is determined in various described ways (counts, percentages) based on a number of described factors (determined threshold voltage distribution, known stored value, past NVM operation event). An extension of the foregoing techniques is described for MLC memory. |