| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8845
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-235
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8828
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-231
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-823
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-71
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-023 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0028
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-845
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0026
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-306
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-20 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C13-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C13-00 |
| filingDate |
2011-12-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2017-05-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2017-05-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-101728934-B1 |
| titleOfInvention |
Non-volatile memory having 3d array of read/write elements with low current structures and methods thereof |
| abstract |
Three-dimensional array read / write (R / W) memory elements are formed over planes of a plurality of layers located at different distances over a semiconductor substrate. It is desirable to operate the R / W elements in low current and high resistance states. The resistance of these resistive states depends on the dimensions of the R / W elements and is predetermined by the process technology. The sheet 400 electrode in series with the R / W device 430 and the method of forming it provide another degree of freedom in regulating the resistance of the R / W memory device 430. The thickness of the sheet electrode 400 is adjusted to obtain reduced cross-sectional contact in the circuit path from the word line 470 to the bit line 440. [ This allows the R / W memory element 430 to have a greater resistance and thus operate with further reduced currents. The sheet electrode 400 is formed without substantially increasing the cell size. |
| priorityDate |
2010-12-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |