| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y40-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y99-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66439
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7803
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y40-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0924
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02587
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-16 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B82B3-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
2011-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2016-04-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2016-04-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-101612658-B1 |
| titleOfInvention |
Semiconductor devices having modulated nanowire counts |
| abstract |
Semiconductor devices with modulated nanowire counts, and methods of forming such devices, are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed on a substrate and stacked within a first vertical plane with a first top nanowire. The second semiconductor device has one or more nanowires disposed on a substrate and having a second highest nanowire stacked in a second vertical plane. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second top nanowires are disposed in the same plane orthogonal to the first and second vertical planes. |
| priorityDate |
2011-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |