http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101608494-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4236 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-2003 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7783 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0605 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8258 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8252 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-072 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66462 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-77 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-778 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-00 |
| filingDate | 2011-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2016-04-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2016-04-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-101608494-B1 |
| titleOfInvention | Group iii-n transistors for system on chip(soc) architecture integrating power management and radio frequency circuits |
| abstract | High F t and also high voltage and / or high power circuits A system-on-chip (SoC) is disclosed that integrates RFICs with PMICs using transistor technology based on group III-nitride (III-N) capable of achieving a breakdown voltage (BV) sufficiently high to implement. In an embodiment, the III-N transistor structure is modifiable for scaling to maintain a trajectory of performance improvement over many successive device generations. In an embodiment, the III-N transistor structure is modifiable for monolithic integration with a Group IV transistor structure, such as planar and non-planar silicon CMOS transistor technology. Planar and non-planar HEMT embodiments having recessed gates, symmetrical sources and drains, regrown source / drains, and the like are formed with a replacement gate technique that allows enhancement mode operation and good gate passivation. |
| priorityDate | 2011-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 38.