| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0214
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-12044
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-19041
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-19043
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-6835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-30105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-561
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-295
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-293
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-568
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3114
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-6835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-562 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-312 |
| filingDate |
2009-04-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2016-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2016-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-101596698-B1 |
| titleOfInvention |
Semiconductor device and method for manufacturing the same |
| abstract |
In a semiconductor integrated circuit sandwiched between a pair of the first and second impact resistant layers, a shock-diffusing layer is provided between the semiconductor integrated circuit and the second shock-resistant layer. By providing the shock-resistant layer against external stress and the shock-diffusing layer for dispersing the impact, the force applied to the semiconductor integrated circuit per unit area is reduced, and the semiconductor integrated circuit is protected. The impact diffusion layer preferably has a low elastic modulus and a high breaking coefficient. |
| priorityDate |
2008-04-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |