http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101588626-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G03F1-62 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28518 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823828 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-105 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G03F1-62 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823814 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823871 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-394 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 |
| filingDate | 2008-10-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2016-02-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2016-02-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-101588626-B1 |
| titleOfInvention | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
| abstract | Methods, structures, and designs are provided for self-aligned local interconnects. The method includes designing diffusion regions to be within the substrate. Some of the plurality of gates are designed to be active gates, and some of the plurality of gates are designed to be formed over the isolation regions. The method includes designing a plurality of gates in a regular and repeating alignment along the same direction, wherein each of the plurality of gates is designed to have dielectric spacers. The method also includes designing a local interconnect layer between the plurality of gates or adjacent the plurality of gates. The local interconnect layer is conductive and disposed on the substrate to permit electrical contact and interconnection to a portion of the active regions of the active gates or to portions of the active regions of the active regions. The local interconnect layer is self-aligned by the dielectric spacers of the plurality of gates. |
| priorityDate | 2007-10-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 37.