| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-05
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-06181
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05572
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-0557
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-0401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-131
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-1305
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-14181
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-1306 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-19
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823871
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 |
| filingDate |
2009-08-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2015-08-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2015-08-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-101546995-B1 |
| titleOfInvention |
Through silicon via and method of fabricating same |
| abstract |
Trench silicon via structure and a method for fabricating the through silicon via. The method includes the steps of: (a) forming a trench 140 in a silicon substrate 100, the trench 140 opening into an upper surface 105 of the substrate 100; (b) forming a silicon dioxide layer 145 on the sidewalls of the trench 140, the silicon dioxide layer not filling the trench 140; (c) filling the remaining space in the trench with polysilicon 160; (d) fabricating at least a portion of the CMOS device (200) on the substrate (100) after step (c); (e) removing the polysilicon from the trench 140, wherein the dielectric layer 145 remains on the sidewalls of the trench; (f) refilling the trench (140) with an electrically conductive core (255); Forming one or more interconnection layers (260) on an upper surface (105) of the substrate (100) after the step (f), wherein one of the one or more interconnection levels closest to the substrate One of the wirings 260 of the wiring level 259 of the conductive layer 255 contacts the conductive core 255. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10790186-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11251070-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101928421-B1 |
| priorityDate |
2008-08-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |