http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101479153-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5283 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53209 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53271 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B99-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8244 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11 |
| filingDate | 2013-05-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2015-01-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2015-01-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-101479153-B1 |
| titleOfInvention | Semiconductor structure and method for forming the same, sram memory unit and sram memory |
| abstract | The present invention relates to a semiconductor structure and a method of forming a semiconductor structure, an SRAM memory unit, and an SRAM memory. The semiconductor structure of the present invention includes at least two adjacent transistors, a conductive layer, and at least two adjacent transistors are formed on a semiconductor substrate; A doped region located between the gate electrodes of two adjacent transistors and the gate electrodes of two adjacent transistors forming a concave portion; The conductive layer covers the bottom of the recess and the side wall. Another semiconductor structure includes a first transistor and a second transistor, a conductive layer, wherein the first transistor and the second transistor are formed on a semiconductor substrate; The insulating layer of the gate electrode of the first transistor covers only a part of the gate electrode layer remote from the second transistor doped region; An insulating layer, a gate electrode layer of the first transistor exposed by the insulating layer, a doped region of the second transistor, and a gate electrode of the second transistor are surrounded to form a concave portion; The conductive layer covers the bottom of the recess and the side wall. The present invention further provides a method of forming the semiconductor structure, an SRAM memory unit comprising the semiconductor structure, and an SRAM memory. According to the present invention, the area of the semiconductor structure can be reduced. |
| priorityDate | 2012-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.