http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101390425-B1

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filingDate 2007-11-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2014-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2014-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-101390425-B1
titleOfInvention Temperature controlled purge gate valve for chemical vapor deposition chamber
abstract The present invention relates to methods and apparatus optimized for manufacturing 3-N (N) compound semiconductor wafers and in particular GaN wafers. In particular, the method substantially prevents the formation of undesired material on an isolation valve fixture in a chemical vapor deposition (CVD) reactor. Particularly, the present invention relates to a method for producing a single crystal III-V group semiconductor material by reacting a predetermined amount of gaseous precursor in the reaction chamber as a reactant with a certain amount of Group 5 elements in a gaseous state as another reactant isolated which provides apparatus and method for limiting the reaction of the deposition / condensation and by-products of the GaCl 3 on the valve. n n Gate Valve, CVD, Mass Production, HVM, Reaction Chamber, Group 3, Group 5, Precision
priorityDate 2006-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 39.