http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101295429-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-028 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-021 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-79 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-004 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-1673 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-1659 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-1675 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0004 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0007 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-003 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C13-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-06 |
| filingDate | 2011-10-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2013-08-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2013-08-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-101295429-B1 |
| titleOfInvention | Semiconductor Memory and Systems |
| abstract | In accordance with the logic of the data held in the real memory cell, the amplifying transistor is reliably turned on or off, and the data is reliably read. The selection transistor and the resistance change element of the real memory cell are connected in series via a connection node between the first voltage line and the second voltage line. In a real amplifying transistor of a real memory cell, a gate, a source, and a drain are connected to a connection node, a reference voltage line, and a real read line, respectively. In the read operation, the gate of the selection transistor receives the read control voltage and a desired voltage is generated at the connection node by resistance division between the selection transistor and the resistance change element. The sense amplifier determines the logic held in the real memory cell in accordance with the voltage of the real read line which changes with the voltage of the connection node. |
| priorityDate | 2010-10-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 29.