http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101151456-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7684 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32138 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B23H5-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-304 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C25F3-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C25F7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32125 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25F3-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-461 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B23H5-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-302 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-304 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3213 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25F7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-321 |
| filingDate | 2003-07-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2012-06-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2012-06-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-101151456-B1 |
| titleOfInvention | Method and System for Proper Electrolytic Polishing and Removal of Barrier Layer and Sacrificial Layer Using Thickness Measurement |
| abstract | The metal layer formed on the semiconductor wafer is appropriately electrolytically polished. A portion of the metal layer is electrolytically polished, wherein portions of the metal layer are each electropolished. Before the electrolytic polishing of the portion, the thickness of the portion of the metal layer to be electrolytically polished is measured. The amount of the portion to be electrolytically polished is adjusted based on the thickness measurement. A metal layer formed on a semiconductor wafer is polished, wherein the metal layer is formed on a barrier layer, the barrier layer is formed on a dielectric layer having a recessed region and a non-recessed region, the metal layer having a recessed region Covering the non-recessed area. The metal layer is polished to remove the metal layer covering the non-recessed region. The metal layer in the recessed region is polished to a height below the non-recessed region, wherein the height is greater than or equal to the thickness of the barrier layer. |
| priorityDate | 2002-07-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID418354341 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID23978 |
Total number of triples: 26.