http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101137950-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28035 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 |
| filingDate | 2005-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2012-05-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2012-05-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-101137950-B1 |
| titleOfInvention | Semiconductor device with dual polysilicon gate and manufacturing method thereof |
| abstract | The present invention is to provide a semiconductor device having a dual polysilicon gate capable of preventing the deterioration of the NMOSFET of the cell while preventing the polysilicon depletion phenomenon, and a method of manufacturing the semiconductor device of the present invention is a NMOSFET Forming a first gate oxide film on a silicon substrate on which a cell region to be formed and a peripheral region on which a PMOSFET and an NMOSFET are to be formed are formed, and an n + polysilicon film and a sacrificial layer implanted with an n-type dopant are formed on the first gate oxide film. Sequentially forming, selectively removing the sacrificial film, the n + polysilicon film and the first gate oxide film formed in the PMOSFET region of the peripheral region, and forming a PMOSFET in the peripheral region where the surface is exposed. Forming a two-gate oxide film, forming a nitride film on the surface of the second gate oxide film, and a second gay film having the nitride film formed thereon Forming a p + polysilicon film thicker than the n + polysilicon film and implanted with a p-type dopant on the oxide film, and performing a gate patterning process on the n + polysilicon film and the p + polysilicon film to form an NMOSFET region of the cell region; And forming an n + polysilicon gate in the NMOSFET region of the peripheral region and forming a p + polysilicon gate in the PMOSFET region of the peripheral region. |
| priorityDate | 2005-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.