http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101120838-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-4061 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-406 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-40615 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-407 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-403 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-403 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-406 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-18 |
| filingDate | 2005-02-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2012-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2012-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-101120838-B1 |
| titleOfInvention | Semiconductor Memory Suitable for Mounting in Mobile Terminals |
| abstract | The trigger generation circuit 104 outputs a trigger signal. The delay circuit 110 receives the trigger signal and outputs a delay signal that delays the trigger signal. The clock counter 106 receives the clock, counts the number of clocks received from receiving the trigger signal until receiving the delay signal, and outputs the count result. The determination circuit 107 stores the correspondence relationship between the number of clocks and the latency, and determines the latency corresponding to the count result output from the clock counter. The latency register 108 holds the determined latency. The WAIT control circuit 109 outputs a WAIT signal to the outside based on the latency held in the latency register 108. n n Synchronous Pseudo SRAM, Refresh, Bank, Clock, Latency, Preamplifier, Enable, Byte Mask, Trigger Signal |
| priorityDate | 2004-02-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 65.