http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101090249-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1214 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1288 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-136 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32134 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76838 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66765 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-136 |
| filingDate | 2004-10-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2011-12-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2011-12-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-101090249-B1 |
| titleOfInvention | Method of manufacturing thin film transistor array panel |
| abstract | First, a gate line having a gate electrode is formed on an insulating substrate, and then a silicon layer, an impurity silicon layer, and a conductor layer are stacked on the gate insulating film covering the gate line. Subsequently, a second portion is disposed in the channel region between the source electrode and the drain electrode on the conductor layer, and is disposed in the wiring region corresponding to the data line and the drain electrode, and having a thickness greater than the first thickness. A photosensitive film pattern having a portion is formed. The conductor layer is etched using the photoresist pattern as an etch mask, and the first portion is removed to reveal the conductor layer in the channel region. Subsequently, a portion of the conductor layer corresponding to the channel region is etched while the silicon layer and the impurity silicon layer corresponding to the remaining region are etched, the conductor layer and the impurity silicon layer positioned in the channel region are removed, and then the second portion is removed. Subsequently, a passivation layer covering a data line and having a contact hole exposing the drain electrode is formed, and a pixel electrode connected to the drain electrode is formed.n n n n Mask, resolution, silicon layer, wiring area, channel area |
| priorityDate | 2004-10-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 19.