http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101059460-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-162 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-12 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-66 |
| filingDate | 2008-10-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2011-08-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2011-08-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-101059460-B1 |
| titleOfInvention | Algorithm Analog-to-Digital Converter |
| abstract | The present invention relates to an algorithm analog-to-digital converter (ADC), wherein the algorithm ADC according to the present invention comprises a flash ADC in a shared structure of a preprocessing amplifier. The number of chips can be reduced by reducing the number. In addition, the power consumption can be minimized by dynamically reducing the bandwidth of the operational amplifier included in the MDAC according to the required resolution.n n n n Algorithm ADC, Dynamic Variable Bandwidth Amplifier, Bias, Flash ADC, MDAC |
| priorityDate | 2008-10-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 16.