http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101045070-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a492183be65153abfa7dec00d51c816 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-2254 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1093 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-022 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-023 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-028 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1066 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1078 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1051 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-22 |
| filingDate | 2010-04-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2011-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_47fa026a5bf0b17d7780b7681bc32bf0 |
| publicationDate | 2011-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-101045070-B1 |
| titleOfInvention | Semiconductor system including semiconductor memory device and semiconductor memory device and method of operating same |
| abstract | A circuit and a method for training and correcting a phase of a write clock and write data applied to a semiconductor memory device, the method comprising: normal training data in which data windows are scanned based on an edge of a source clock in response to a training input command. And a first data input / output section for outputting the edge of the data window to the edge of the source clock in response to the training output command, and recovering the recovery information training data-the edge of the source clock in response to the training input command. A data window is scanned as a reference, and provides a second data input / output section for outputting the edge of the data window in synchronization with the edge of the source clock in response to the training output command, and normal data and A semiconductor memory device into which recovery information data is input / output; A semiconductor system having a semiconductor memory device controller, the recovery information training data being transmitted to a semiconductor memory device at a first time point set corresponding to a training input command generated therein, and set according to a training output command generated therein. A semiconductor memory device controller for adjusting a phase of recovery information data transmitted to the semiconductor memory device in response to the feedback recovery information training data applied from the semiconductor memory device at a second time point, and recovering at a first time point corresponding to the training input command; The semiconductor memory device which receives the information training data from the semiconductor memory device controller and transmits the information training data to the semiconductor memory device controller as feedback recovery information training data at a second time point set corresponding to the training output command. It provides a system including a semiconductor. |
| priorityDate | 2010-04-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 37.