http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100990396-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01079 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01078 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-09701 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-48 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48 |
| filingDate | 2008-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2010-10-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2010-10-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100990396-B1 |
| titleOfInvention | Laminated Wafer Level Packages and Manufacturing Methods Thereof |
| abstract | The present invention discloses a laminated wafer level package and a method of manufacturing the same. The laminated wafer level package is formed by bonding a solder ball for interconnection of a component to be laminated to a conductive layer for forming a rearranged wiring layer in advance, and then performing a semiconductor chip mounting process, a rearranged wiring layer forming process, and a lamination process. Misalignment problems occurring in the lamination process can be improved, thereby improving reliability and yield and reducing manufacturing costs.n n n n Wafer Level Package, Stacked, Solder Ball, Misaligned, Interconnect |
| priorityDate | 2008-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 21.