http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100977339-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-2024 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B60R2011-0066 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B60Y2304-07 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B60R21-2037 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0804 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B62D1-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0893 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0864 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-41 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-15 |
| filingDate | 2004-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2010-08-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2010-08-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100977339-B1 |
| titleOfInvention | Semiconductor devices |
| abstract | If the memory capacity of the memory is increased by using the conventional SRAM, the chip size becomes large and the cost increases. Further, there has been a problem that the data holding current increases. SESO memory or phase change memory having a smaller memory cell area than SRAM are used. It has a plurality of memory banks composed of SESO, phase change memory and the like. A cache memory composed of the number of ways of the ratio (m / n) of the write speed m and the read speed n is used. The rewrite operation from the cache is controlled so as not to continue in the same memory bank. By using a highly integrated memory cell, a memory having a large data storage capacity can be realized without increasing the chip size. A memory with a small data holding current can be realized. By using a small amount of cache memory, it is possible to realize a data processing system in which external access is not delayed even when a memory having a slow writing speed is used.n n n n Memory Banks, Cache Memory, Data Buses, I / O Nodes, Memory Cells |
| priorityDate | 2003-05-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 25.