http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100971325-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-60 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76873 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7687 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 |
| filingDate | 2008-09-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2010-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2010-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100971325-B1 |
| titleOfInvention | MIM capacitor manufacturing method of semiconductor device |
| abstract | The present invention relates to a method for manufacturing a MIM capacitor of a semiconductor device for producing a capacitor from the upper metal and the lower metal in a multi-layer metal wiring process using copper metal as a wiring material.n n n The method of manufacturing a MIM capacitor of a semiconductor device of the present invention performs a photolithography process and an etching process to form a cavity pattern in a MIM formation region by selectively removing a first insulating film and a diffusion barrier layer on a semiconductor substrate on which a lower metal wiring is formed. step; A second step of forming a copper film by sequentially depositing a lower conductive layer, a dielectric film, an upper conductive layer, and a copper seed film, followed by an electrochemical plating process; Performing a chemical mechanical polishing process to remove a copper film, an upper conductive layer, a dielectric film, and a lower conductive layer except for the cavity pattern; A fourth step of partially etching the lower conductive layer and the upper conductive layer; A fifth step of sequentially depositing a diffusion barrier film and a second insulating film; After the photolithography process and the etching process are performed to pattern the trench pattern and the via contact hole, the barrier metal and the copper seed layer are deposited, and then the electrochemical plating process and the chemical mechanical polishing process are performed to form the upper metal wiring. It characterized by comprising;n n n According to the method of manufacturing a MIM capacitor of a semiconductor device according to the present invention, capacitance value can be increased by using existing equipment and processes without considering new equipment investment and additional processes.n n n n MIM Capacitors, Copper Inlay, Capacitance |
| priorityDate | 2008-09-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 18.