http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100942739-B1

Outgoing Links

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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407
filingDate 2003-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2010-02-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2010-02-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-100942739-B1
titleOfInvention Semiconductor memory
abstract An object of the present invention is to reduce power consumption during operation of a semiconductor memory while maintaining high speed operation without increasing the chip size. n The pulse generation circuit generates a column pulse a plurality of times in response to the read command. The address counter sequentially outputs an address subsequent to the external address supplied in response to the read command as an internal address. The column decoder sequentially selects column select lines in synchronization with column pulses. Multiple bits of data read from the memory cell in response to one read command are sequentially transferred to the common data bus line through the column switch. As a result, the number of data bus lines can be minimized and the increase in chip size can be prevented. Since a plurality of bits of data can be transferred on one data bus line, the memory area to be activated in response to the read command can be minimized. As a result, power consumption can be reduced.
priorityDate 2002-08-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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Total number of triples: 24.