http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100885487-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-109 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-0175 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1084 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1087 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 |
| filingDate | 2007-07-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2009-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2009-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100885487-B1 |
| titleOfInvention | Input device of semiconductor memory device |
| abstract | The present invention is to provide an input device of a semiconductor memory device capable of stably recognizing a signal even in the case of PVT fluctuations. To this end, the present invention is activated by a drive signal to buffer a positive / negative input signal and positive / negative free. First buffer means for outputting an internal input signal; Second buffer means activated by the driving signal to buffer the positive / negative pre-internal input signal and output the positive internal input signal; And a third buffer means which is activated by the driving signal and buffers the positive / negative pre-internal input signal to output the negative internal input signal.n n n n Input Buffer, 2-Stage, Differential Input, Delay, Timing Margin |
| priorityDate | 2007-07-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 36.